1. Field of the Invention
The present invention relates to semiconductor memory devices and, more particularly, to a semiconductor memory device having a multilevel interconnection structure.
2. Description of the Related Art
Hitherto, this kind of semiconductor memory device includes a DRAM in which a memory chip is divided into banks, each bank is divided into subblocks, and then, each subblock has a plurality of memory mats arranged in a matrix form. In the DRAM with the above structure, sense amplifier (SA) areas are arranged along two opposite sides of each memory mat, at least one sub-word driver (SWD) area is disposed along another or two other opposite sides thereof. It is assumed that the SA areas are arranged on both sides of each memory mat in parallel to word lines (namely, in the X direction) and the SWD areas are arranged so as to intersect the X direction. In other words, the SWD areas are arranged in the Y direction in parallel to each other and the SA areas are arranged in the X direction in parallel to each other. Column selection lines YS extend in the Y direction.
To meet the demands of large scale integration, the following attempt is being made in the above-mentioned DRAM: Circuits for controlling or driving sense amplifier circuits and sub-word driver circuits are arranged in intersection areas (hereinbelow referred to as crossing areas) of the SA areas and the SWD areas because the crossing areas are not used as the SA areas and the SWD areas. Accordingly, the crossing areas can be used effectively. The arrangement of the SWD areas and the effective use of the crossing areas result in the high-speed operation of the DRAM.
Further, according to recent trends, in order to respond to requests to reduce the size of a chip, various lines are arranged not only between the adjacent memory mats but also over the memory mats. For example, lines including power lines, local input/output lines LIO, main input/output lines MIO, and signal lines are arranged on different layers so as to form a mesh pattern (hereinbelow referred to as a mesh arrangement). The mesh arrangement is becoming more widely used.
As this type of semiconductor memory device, for example, Japanese Unexamined Patent Publication (JP-A) No. 2002-15578 (hereinbelow, referred to as a first cited document) discloses a DRAM. For the array structure of the DRAM, a divided word driver (DWD) system is used and a hierarchical structure (multilevel interconnection) is used. In other words, input/output lines such as local I/O lines LIO, global input/output lines GIO, and similar lines are arranged on different layers. In addition, the first cited document includes an arrangement in which a sub-amplifier or a CMOS switch is disposed in a crossing area.
The multilevel interconnection on each of the memory mats of the DRAM disclosed in the first cited document will now be specifically described. As shown in FIG. 8 contained in the first cited document, the multilevel interconnection on the memory mat include word lines, bit lines, and capacitors. The word lines are integrated with the gate electrodes of respective MOSFETs formed in a substrate. The bit lines are formed above the word lines, with an insulating film therebetween. The bit lines are connected to a diffusion layer. The bit lines are formed in a first metal layer (hereinbelow, referred to as an M1 layer). The capacitors are connected to the diffusion layer. The capacitors are arranged above the bit lines. The capacitors are connected to a plate electrode. In this case, the M1 layer includes a polysilicon layer FG serving as a first layer and sub-word lines SWL.
A second metal layer (hereinbelow, referred to as an M2 layer) including main word lines MWL is arranged on the plate electrode. A third metal layer serving as a top layer (hereinbelow, referred to as an M3 layer) is further arranged on the M2 layer. The M3 layer includes column selection lines YS. The multilevel interconnection structure is formed as mentioned above. In the M3 layer, the column selection lines YS extend in the Y direction, namely, parallel to columns. In the M2 layer, the main word lines MWL extend parallel to rows so as to intersect the Y direction, namely, in the X direction.
On the other hand, the multilevel interconnection in each of sub-word driver (SWD) areas will now be described. The SWD areas each have a sub-word driver included in peripheral circuits surrounding the memory mat. This multilevel interconnection comprises the M2 layer and the M3 layer. The M2 layer includes the main word lines MWL, X-direction signal lines (arranged parallel to the word lines), and meshed power lines. These lines are arranged in the X direction. The M3 layer includes sub-word-selection signal lines FXT and FXB to select a word line, power lines used in the SWD area, power lines used for circuits in the adjacent crossing area, and main I/O lines MIO. These lines are arranged in the Y direction.
As mentioned above, the first cited document discloses the following structure: In the memory mats and the SWD areas for the peripheral circuits, the main word lines MWL are arranged in the X direction in the M2 layer under the M3 layer. On the other hand, the column selection lines YS and the sub-word-selection signal lines FXT and FXB are arranged in the Y direction in the M3 layer on the M2 layer. The lines YS and the lines FXT and FXB are needed for the memory mats and the SWD areas.
It turns out that when the main word lines MWL are arranged in the X direction in the M2 layer over the memory mats and the SWD areas, the arrangement of the lines in the SWD areas is limited. Specifically speaking, it is necessary to arrange the sub-word-selection signal lines FXT and FXB to select a word line and the power lines in each SWD area. The lines FXT and FXB and the power lines have to be electrically connected to the sub-word lines SWL arranged in the M1 layer.
In the multilevel interconnection structure in which the sub-word-selection signal lines FXT and FXB and the power lines are arranged in the M3 layer (top layer), therefore, it is necessary to electrically connect the sub-word-selection signal lines FXT and FXB and the power lines in the M3 layer to the sub-word lines SWL in the M1 layer through the M2 layer in the SWD area. In addition, it is necessary to electrically connect the sub-word-selection signal lines FXT and FXB and the power lines in the M3 layer to the diffusion layer and the gates under the M1 layer. In this instance, it is necessary to consider that the number of sub-word-selection signal lines FXT and FXB is larger than the number of main word lines MWL and the number of lines FXT and FXB is also larger than the number of sub-word lines SWL.
Accordingly, in the M2 layer, it is necessary to form a pattern of islands for connecting the lines FXT and FXB in the M3 layer to the lines SWL in the M1 layer. It is also necessary to arrange the lines for connection in the SWD area in the M2 layer. In other words, in the M2 layer in the SWD area, it is necessary to form islands for electrically connecting the lines FXT and FXB to the M1 layer in addition to the lines MWL, the X-direction signal lines, and the meshed power lines. In this case, the following technique is used in the SWD area: In the M2 layer, the lines MWL, the X-direction signal lines, and the meshed power lines are arranged so as to avoid the islands connected to the lines FXT and FXB. Accordingly, in the multilevel interconnection structure disclosed in the first cited document, the number of lines other than the lines MWL in the M2 layer is limited by the islands formed in the M2 layer and the lines for connection in the SWD area.
The following are considered to be the disadvantages of the above-mentioned conventional array interconnection structure: As the integration density of the DRAM becomes higher in the future, the size of each array will become larger and the number of circuits arranged in each crossing area will also become larger. Accordingly, the number of signal lines for driving these circuits will also increase. The number of power lines used in the array will also increase because the low-voltage operation is desired. These signal lines and the array power lines principally extend from row decoders XDEC between the main word lines MWL in the X direction, thus supplying signals and power to the memory mats. In the above-mentioned interconnection structure, since the number of lines in the X direction is limited, it may not be possible to arrange the necessary signal lines and power lines.
FIG. 12 shows a conventional multilevel interconnection structure. The problems of this structure will now be described with such a specific example. Referring to FIG. 12, lines are arranged in the M2 and M3 layers in a memory mat. In the conventional array structure, as shown in FIG. 12, the lines MWL are arranged in the X direction in the M2 layer and the lines YS are arranged in the Y direction in the M3 layer.
In this interconnection structure, it is assumed that the size of the memory mat is 512xc3x97512 bits and eight sub-word lines are provided for every main word line (8SWL/1MWL) in the arrangement of each of the SWD areas. Accordingly, the number of lines MWL arranged in the memory mat is 64 (512/8). In the actual interconnection, for the number of X-direction signal lines (parallel to the rows) and array power lines (meshed lines) capable of passing through the SWD area, only one line is arranged per two lines MWL. The reason is that the islands are formed in the M2 layer in the SWD areas and the layout of lines in the M2 layer is limited. Therefore, the number of meshed lines is 32.
On the other hand, in the circuits of the memory mat, the necessary number of signal lines and power lines extending from the row decoder XDEC in the array is 52 per memory mat, as is obvious from TABLE in FIG. 12. However, it is impossible in the conventional layout because only 32 lines can be arranged in the conventional array structure.
The above-mentioned interconnection structure is conventionally used. According to the structure, the lines extending parallel to the column selection lines YS (in the YS direction) are arranged in the top layer and the lines extending parallel to the main word lines MWL are arranged in the layer (lower layer) under the top layer. The main I/O lines MIO are arranged in the YS direction in the top layer (M3 layer). In the interconnection structure, the flexibility of the meshed lines arranged parallel to the main word lines MWL, namely, in the X direction, is low. The lines have to be arranged according to a predetermined rule.
In other words, in the case of disposing the lower layer (M2 layer) parallel to the main word lines (in the X direction), it is necessary to use the lower layer (M2 layer) for the interconnection in the sub-word drivers, thus limiting the layout of the meshed lines arranged parallel to the main word lines MWL in the array. Therefore, only one line is arranged between the two main word lines MWL.
In addition to the power lines for the memory mat or array, signal lines for circuits in the crossing areas may be arranged along the main word lines MWL in some cases. In other words, the number of lines arranged along the lines MWL is larger than that arranged along the lines YS. In the conventional interconnection structure, when the number of signal lines increases owing to a change in the circuits in the crossing areas, the increased number of lines may affect the chip size.
As mentioned above, in the conventional memory device, the arrangement in the M2 layer including the lines MWL on the memory mats (memory arrays) extends over the SWD areas and the SA areas serving as the peripheral circuits. In fact, the disadvantages of this structure are not taken into consideration.
It is an object of the present invention to provide a semiconductor memory device in which the conventional disadvantages are overcome. These disadvantages are caused when an interconnection structure on memory mats (memory arrays) extends over areas for sub-word drivers and sub-amplifiers serving as peripheral circuits.
Another object of the present invention is to provide a semiconductor memory device having an interconnection structure capable of sufficiently coping with an increase in the number of signal lines and power lines in the future.
Further another object of the present invention is to provide a semiconductor memory device having a layout in which the arrangements of lines used in a conventional array structure are transposed with each other.
According to the present invention, an interconnection structure includes a top layer (a third metal layer: M3 layer) extending along main word lines and a lower layer (second metal layer: M2 layer) extending along column selection lines. Main input/output lines are arranged parallel to the main word lines in the M3 layer. The top layer is not used to connect lines in sub-word drivers. Thus, each interval between meshed lines, arranged between the main word lines, can be increased. Consequently, on the top layer in the interconnection structure, power lines and signal lines are arranged along the main word lines in arrays with high efficiency. The flexibility of the layout of meshed lines can be increased and the chip size can be reduced.
Further, aspects of the present invention will now be described hereinbelow.
According to an aspect of the present invention, there is provided a semiconductor memory device including: a plurality of memory mats each including a plurality of memory cells arranged along columns and along rows, the columns being arranged in the Y direction and the rows being arranged in the X direction; sense amplifier areas arranged around each memory mat so as to intersect the Y direction; and sub-word driver areas arranged around each memory mat so as to intersect the X direction, wherein column selection lines and main word lines are arranged on the memory mats, the column selection lines extending in the Y direction, the main word lines extending in the X direction, and a layer including the column selection lines is disposed under a layer including the main word lines.
In this aspect, preferably, each of the sub-word driver areas includes a layer including sub-word selection lines and the layer including the main word lines, and the layer including the main word lines is disposed on the layer including the sub-word selection lines.
Preferably, a layer including sub-word lines is arranged as a first metal layer under the layer including the sub-word selection lines, and the layer including the sub-word selection lines is disposed as a second metal layer.
Preferably, the main word lines are arranged in the X direction at predetermined intervals, the layer including the main word lines is arranged as a third metal layer on the second metal layer, and the third metal layer further includes a power line extending in the X direction between the adjacent main word lines.
Preferably, a plurality of power lines are arranged between the adjacent main word lines.
Preferably, the first metal layer includes a pattern of islands connected to the sub-word selection lines.
Preferably, each of the sense amplifier areas includes a first metal layer including bit pair lines extending in the Y direction and a second metal layer including the column selection lines, and the second metal layer including the column selection lines is disposed on the first metal layer.
Preferably, each of the sense amplifier areas has device regions constituting sense amplifiers arranged in a layer under the first metal layer, a third metal layer including power lines and signal lines electrically connected to the device regions is arranged on the second metal layer, and the power lines and the signal lines in the third metal layer extend in the X direction.
Preferably, the second metal layer including the column selection lines has a pattern of islands through which the power lines and the signal lines in the third metal layer connect to the device regions.
Preferably, the pattern of islands is formed in the second metal layer so as to correspond to sense-amplifier drive lines arranged in the third metal layer, and the islands are connected to the respective sense-amplifier drive lines.
Preferably, the semiconductor memory device according to this aspect further has crossing areas which are arranged around each memory mat and where the sense amplifier areas and the sub-word driver areas are not formed. Each of the crossing areas may include first lines connected to the lines arranged in the adjacent sub-word driver area and second lines connected to the lines arranged in the adjacent sense amplifier area.
Preferably, the first lines are arranged in a layer under a layer including the second lines.
Preferably, the first lines include sub-word selection lines connected to the sub-word selection lines arranged in the adjacent sub-word driver area and power lines, and the second lines include power lines for driving the sense amplifiers in the adjacent sense amplifier area.
Preferably, the semiconductor memory device according to this aspect further includes crossing areas which are arranged around each memory mat and where the sense amplifier area and the sub-word line area are not formed. Each of the crossing areas may include a sub-amplifier connected to sense amplifiers arranged in the adjacent sense amplifier area.
Preferably, the semiconductor memory device further includes crossing areas which are arranged around each memory mat and where the sense amplifier areas and the sub-word line areas are not formed. Each of the crossing areas may include a CMOS switch.
According to another aspect of the present invention, there is provided a semiconductor memory device including: sub-word driver areas including main word lines and sub-word selection lines, wherein a layer including the sub-word selection lines is disposed under a layer including the main word lines.
Preferably, in this aspect, the main word lines are arranged at intervals and extend in the X direction so as to connect to main word lines of memory mats, and the sub-word selection lines are arranged in the layer under the layer including the main word lines and extend in the Y direction intersecting the X direction.
Preferably, sub-word lines are arranged in the X direction in a layer under the layer including the sub-word selection lines.
Preferably, a plurality of power lines are arranged in the X direction between the adjacent main word lines.